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d a t a sh eet product speci?cation file under integrated circuits, ic21 august 1993 integrated circuits p90ce201 16-bit microcontroller
august 1993 2 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 contents 1 features 2 general description 3 ordering information 4 pinning information 4.1 pinning 4.2 pin description 5 cpu functional description 5.1 general 5.2 5.2 programming model and data organization 5.3 internal and external operation 5.4 processing states and exception processing 5.5 stack format 5.6 cpu interrupt processing 6 system control 6.1 memory mapping 6.2 interrupt controller 6.3 system control registers 6.4 reset 6.5 clock circuitry 7 instruction set 7.1 addressing modes 7.2 instruction timing 8i 2 c-bus interface 8.1 general 8.2 i 2 c-bus interface registers 9 uart serial interface 9.1 general 9.2 operating modes 9.3 uart registers 10 8-bit general port 10.1 8-bit general port registers 11 8-bit auxiliary port 11.1 8-bit auxiliary port registers 12 watchdog timer 13 timers 13.1 general 13.2 timer operating modes 13.3 timer registers 14 electromagnetic compatibility (emc) improvements 15 electrical specifications 15.1 limiting values 15.2 dc characteristics 15.3 ac characteristics 16 register map 17 package outline 18 soldering 18.1 introduction 18.2 reflow soldering 18.3 wave soldering 18.4 repairing soldered joints 19 definitions 20 life support applications 21 purchase of philips i 2 c components
august 1993 3 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 1 features cmos technology full 68000 software compatibility 32-bit internal structure 16-bit internal data transfer 8-bit access to external rom/ram external addressing range 16 mbytes for rom and 16 mbytes for ram unused address pins can be used as quasi-bidirectional ports on-chip address decoder for rom/ram 8 edge triggered programmable interrupts that can also be used as quasi-bidirectional ports reset control built-in clock generator 2 fully independent fast i 2 c-bus serial interfaces uart serial interface (4 modes) 3 fully independent 16-bit timers watchdog timer 8-bit quasi-bidirectional port, 4-bits with high drive capability emc optimized layout and pinning 64-pin qfp package 2 general description the p90ce201 is a member of the p9xcxxx family of highly integrated 16-bit microcontrollers for use in a wide variety of applications. it is fully software compatible with the 68070/68000. the complete set of system functions available on the chip results in reduced system cost. additionally, its modular design concept permits future extension to the family. 3 ordering information note 1. sot319-2; 1996 november 28. extended type number package clock frequency (mhz) temperature range ( c) pins pin position material code P90CE201AEB 64 qfp plastic sot319 (1) 24.0 - 25 to 85
august 1993 4 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 fig.1 block diagram 1. the general port lines gp5, gp6 and gp7 have alternate functions for timer 1, scl1 and sda1 respectively; see table 1. mlb015 address decoder address buffer data interface port timer 0 ocd (15 : 0) timer 1 timer 2 uart i c 1 2 i c 2 2 interrupt controller reset logic clock oca (31 : 0) cpu system control watchdog timer reset xtal1 xtal2 intn0 - intn7 sda2 scl2 rxd txd t2 t0 r/wn d0-d7 a16-a23 a0-a15 gp0-gp7 csramn csromn (1)
august 1993 5 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 4 pinning information 4.1 pinning fig.2 pin configuration for qfp64. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 20 21 22 24 25 26 27 28 29 30 31 32 23 64 63 62 60 59 58 57 56 55 54 53 52 61 rxd sda2 scl2 gp7/sda1 gp6/scl1 gp0 gp1 gp2 gp3 gp4 gp5/t1 a23/ap7 a22/ap6 a21/ap5 a20/ap4 xtal2 xtal1 v dd1 v ss1 r/wn a19/ap3 a18/ap2 a16/ap0 a17/ap1 a15 a14 a12 a13 a7 a8 a6 a9 a5 a11 a4 csromn a3 a10 a2 a1 d7 a0 d6 d0 d5 d1 d4 d2 d3 csramn v ss2 v dd2 reset t0 t2 lp0/intn0 lp1/intn1 lp2/intn2 lp3/intn3 lp4/intn4 lp5/intn5 lp6/intn6 lp7/intn7 txd p90ce201 mlb003
august 1993 6 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 4.2 pin description table 1 qfp64 package. mnemonic type pin no. function rxd i/o 1 receive data. rxd is the data input for the uart interface. sda2 i/o 2 serial data 2 (open drain). sda2 is the data signal for the second i 2 c-bus serial interface. scl2 i/o 3 serial clock 2 (open drain). scl2 is the clock signal for the second i 2 c-bus serial interface. gp7/sda1 gp6/scl1 gp0 gp1 gp2 gp3 gp4 gp5/t1 i/o 4 5 6 7 8 9 10 11 general purpose port (active high, 3-state). the alternative functions are as follows. scl1 is the clock signal for the ?rst i 2 c-bus serial interface. sda1 is the data signal for the ?rst i 2 c-bus serial interface. t1 is the input pin for timer 1. a23/ap7 to a16/ap0 i/o 12 to 15, 21, 22, 24, 23 address bus. upper 8-bits of the address bus (a23 to a16). the unused address bits can be selected as a quasi-bidirectional port (ap). a15 to a0 o 25, 26, 28, 27, 34, 38, 32, 30, 29, 31, 33, 35, 37, 39, 40, 42 address bus. lower 16-bits of the address bus. xtal2 o 16 oscillator output. not connected if an external clock generator is used. xtal1 i 17 oscillator input. xtal1 can also be used as an external clock input if an external clock generator is used. v dd1 - 18 supply voltage. for internal logic, address bus, data bus, rwn, csramn, csromn, xtal1 and xtal2. v ss1 - 19 ground. for internal logic, address bus, data bus, rwn, csramn, csromn, xtal1 and xtal2. r/wn o 20 read (active high)/ write (active low). this controls the direction of data ?ow. csromn o 36 chip select rom (active low). this signal selects external rom. d0 to d7 o 44, 46, 48, 49, 47, 45, 43, 41 data bus. 8-bit data bus. csramn o 50 chip select ram (active low). this signal enables external ram. v ss2 - 51 ground. for all other periphery pins (quiet port). v dd2 - 52 supply voltage. for all other periphery pins (quiet port). reset i 53 reset (active high). input pin for an external reset. t0 i 54 timer 0. input pin for cycle and event counting using timer 0. t2 i 55 timer 2. input pin for cycle and event counting using timer 2.
august 1993 7 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 lp0/intn0 lp1/intn1 lp2/intn2 lp3/intn3 lp4/intn4 lp5/intn5 lp6/intn6 lp7/intn7 i/o 56 57 58 59 60 61 62 63 latched interrupt inputs (active low). a low level of 3 1 clock pulse will be stored as a pending interrupt request. priority levels are programmable. unused interrupt inputs can be used as a quasi-bidirectional port (lp). txd o 64 transmit data. txd is the data output for the uart serial interface. mnemonic type pin no. function
august 1993 8 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 5 cpu functional description 5.1 general the cpu of the p90ce201 is software compatible with the 68000, consequently programs written for the 68000 will run on the p90ce201 unchanged. however, for certain applications the following differences between the processors should be noted: the initialization of the system control registers. differences exist in the address error exception processing since the p90ce201 can provide full error recovery. the timing is different because of the p90ce201s new architecture and technology. the instruction execution timing is completely different for the same reason. 5.2 5.2 programming model and data organization the programming model is identical to that of the 68000 and is shown in fig.3. it contains seventeen 32-bit registers, a 32-bit program counter and a 16-bit status register. the first eight registers (d0 to d7) are used as data registers for byte, word and long-word operations. the second group of registers (a0 to a6) and the system stack pointer (a7) can be used as software stack pointers and base address registers. in addition, these registers can be used for word and long-word address operations. all seventeen registers can be used as index registers. the p90ce201 supports 8, 16 and 32-bit integer data, bcd data 32-bit addresses. each data type is arranged in memory as shown in fig.4. fig.3 programming model. handbook, full pagewidth eight data registers program counter two stack pointers seven address registers a6 a0 31 16 15 8 7 0 do d1 d2 d3 d4 d5 d6 d7 user stack pointer supervisor stack pointer a7 31 16 15 0 a1 a2 a3 a4 a5 31 0 status register system byte user byte 15 8 7 0 mcd504
august 1993 9 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 fig.4 memory data organization. (f) bcd data (2 bcd digits = 1 byte). (d) long-word data (32 bits). msb high order low order lsb 1514131211109876543210 bit high order low order high order low order (c) word data (16 bits). msb word 0 word 1 lsb 1514131211109876543210 bit word 2 (b) integer data (1 byte = 8 bits). msb byte 0 byte 2 lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit byte 1 byte 3 bcd 0 bcd 1 bcd 4 bcd 5 bcd 2 bcd 3 bcd 6 bcd 7 msb lsb 1514131211109876543210 bit mcd505 (e) addresses (1 address =32 bits). msb high order low order lsb 1514131211109876543210 bit high order low order high order low order (a) bit data (1 byte = 8 bits). 2 7 6543 1 0 bit long word 0 long word 1 long word 2 address 0 address 1 address 2
august 1993 10 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 fig.5 status register. handbook, full pagewidth trace mode interrupt mask extend negative zero overflow carry t s 121110 x n z v c supervisor state 0 4 8 10 13 15 bit mcd506 5.3 internal and external operation the p90ce201 operates with an internal clock frequency of half the oscillator frequency (f osc /2). each internal clock cycle is divided into 2 states. a non-access machine cycle has 3 clock cycles or 6 states (s0 to s5). a minimum bus cycle normally consists of 3 clock cycles (6 states). when data transfer has not yet been terminated, wait states (sw) are inserted in multiples of 2. for external memory access, 2 wait states (bus states sb) are added automatically. 5.4 processing states and exception processing the cpu is always in one of three processing states: normal, exception or halted. the normal processing state is that associated with instruction execution; the memory references are to fetch instructions and operands and to store results. a special case of the normal state is the stopped state which the processor enters when a stop instruction is executed. in this state the cpu makes no further memory references. the exception processing state is associated with interrupts, trap instructions, tracing and other exceptional conditions. the exception may be generated internally by an instruction or by an unusual condition arising during the execution of an instruction. externally, exception processing can be forced by an interrupt or a reset. the halted processing state is an indication of a catastrophic hardware failure. for example, if during exception processing of a bus error another bus error occurs, the cpu assumes that the system is unusable and halts. only an external reset can restart a halted processor. note that a cpu in the stopped state is not in the halted state or vice versa. the processor can work in the user or supervisor state determined by the state of the s-bit in the status register. accesses to the on-chip peripherals are achieved in the supervisor state. all exception processing is performed in the supervisor state once the current content of the status register has been copied. the exception vector number is then determined and copies of the status register, the program counter value and the format/vector number are saved on the supervisor stack using the supervisor stack pointer. finally, the contents of the exception vector location is fetched and loaded into the program counter.
august 1993 11 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 5.4.1 e xception vectors exception vectors are memory locations from which the cpu fetches the address of a routine that will handle that exception. all exception vectors are 2 words long (see fig.6) except for the reset vector which is made up of 4 words, containing the program counter (pc) and the supervisor stack pointer (ssp). all exception vectors are contained in the supervisor data space. a vector number is an 8-bit number that, when multiplied by 4, gives the address of an exception vector. vector numbers are generated internally. the memory map for the exception vectors is given in table 2. fig.6 exception vector format. handbook, halfpage new program counter (high) new program counter (low) word 0 word 1 mcd509
august 1993 12 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 2 exception vector assignment. note 1. vectors 12, 13, 16 to 23 and 48 to 63 are reserved for future enhancements. no user peripheral devices should be assigned to these numbers. vector no. dec hex assignment 0 0 000 reset: initial ssp 1 4 004 reset: initial pc 2 8 008 bus error 3 12 00c address error 4 16 010 illegal instruction 5 20 014 zero divide 6 24 018 chk instruction 7 28 01c trapv instruction 8 32 020 privilege violation 9 36 024 trace 10 40 028 line 1010 emulator 11 44 02c line 1111 emulator 12 48 030 unassigned, reserved 13 (note 1) 52 034 unassigned, reserved 14 56 038 format error 15 60 03c uninitialized interrupt vector 16 to 23 (note 1) 64 - 92 040 - 05c unassigned, reserved 24 96 060 spurious interrupt 25 100 064 level 1 on-chip interrupt autovector 26 104 068 level 2 on-chip interrupt autovector 27 108 06c level 3 on-chip interrupt autovector 28 112 070 level 4 on-chip interrupt autovector 29 116 074 level 5 on-chip interrupt autovector 30 120 078 level 6 on-chip interrupt autovector 31 124 07c level 7 on-chip interrupt autovector 32 to 47 128 - 188 080 - 0bc trap instruction vectors 48 to 63 (note 1) 192 - 252 0c0 - 0fc unassigned, reserved 64 to 255 256 - 1020 100 - 3fc user interrupt vectors
august 1993 13 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 5.4.2 m ultiple exceptions as two or more exceptions can occur simultaneously, exceptions are grouped in order of priority; as is shown in table 3. 5.4.3 i nstruction traps traps are exceptions caused by instructions arising either from cpu recognition of abnormal conditions during instruction execution or from instructions whose normal behaviour is to cause traps. some instructions are used specifically to generate traps. the trap instruction always forces an exception, and is useful for implementing system calls for user programs. the trapv and chk instructions force an exception if the user program detects a run-time error, possibly an arithmetic overflow or a subscript out of bounds. the signed divide (divs) and unsigned divide (divu) instructions will force an exception if a divide-by-zero operation is attempted. 5.4.4 i llegal and unimplemented instructions illegal instruction is the term used to refer to any word that is not the first word of a legal instruction. during instruction execution, if such an instruction is fetched, an illegal instruction exception occurs. words with bits 15 to 12 equal to 1010 or 1111 are defined as unimplemented instructions and separate exception vectors are allocated to these patterns for efficient emulation. this facility allows the operating system to detect program errors, or to emulate unimplemented instructions in software. 5.4.5 p rivilege violations to provide system security, various instructions are privileged and any attempt to execute one of the privileged and any attempt to execute one of the privileged instructions while the cpu is in the user state causes an exception. the privileged instructions are: stop reset rte move to sr and (word) immediate to sr eor (word) immediate to sr or (word) immediate to sr move usp. 5.4.6 t racing the cpu includes a facility to trace instructions one by one to assist in program development. in the trace state, after each instruction is executed, an exception is forced so that a debugging program can monitor execution of the program under test. the trace facility uses the t-bit in the supervisor part of the status register. if the t-bit is cleared, tracing is disabled and instructions execute normally. if the t-bit is set at the beginning of the execution of an instruction, a trace exception will be generated after that instruction is executed. if the instruction is not executed, either because of an interrupt, or because the instruction is illegal or privileged, the trace exception does not occur. also, the trace exception does not occur if the instruction is aborted by a reset, bus error, or address error exception. if the instruction is executed and an interrupt is pending, the trace exception is processed before the interrupt. if the execution of an instruction forces an exception, the forced exception is processed before the trace exception. as an extreme illustration of the above rules, consider the arrival of an interrupt during the execution of a trap instruction while tracing is enabled. first the trap exception is processed, then the trace exception, and finally the interrupt is processed. instruction execution resumes in the interrupt handling routine. table 3 exception grouping and priority. group exception processing 0 reset, address error bus error exception processing begins at the next machine cycle. 1 trace, interrupt, illegal, privilege exception processing begins before the next instruction. 2 trap, trapv, chk, zero, divide, format error exception processing is started through normal instruction execution.
august 1993 14 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 5.5 stack format the stack format for exception processing is similar to the 68010 (rather than the 68000) although the information stored is not the same due to the different architecture. to handle this format the p90ce201 differs from the 68000 in that: the stack format has changed. the minimum number of words put into, or restored from, the stack is 4 (68010 compatible; not 3 as with the 68000). the rte instruction decides (with the aid of the 4 format bits) whether or not more information has to be restored. the p90ce201 long format is used for bus error and address error exceptions; all other exceptions use the short format. if another format code, other than one of the two listed above, is detected during the restore action, a format error occurs. if the user wants to finish the instruction in which the bus or address error occurred, the p90ce201 format must be used on rte. if no changes to the stack are required during exception processing, the stack format is transparent to the user. 5.5.1 l ong and short stack formats fig.7 stack format. sr status register. pch/pcl program counter high/low word. format indicating either a short stack (only the ?rst 4 words), or the long stack format for bus and address error exceptions. see fig.9. vector number the vector number of the exception in the vector table; e.g. 2 for a bus error and 3 for an address error. see fig.9. ssw special status word; see fig.8. mm current move multiple mask. tdph/tdpl in the event of a faulty write cycle, the data can be found here. tpfh/tpfl the address used during the faulty bus cycle. dbinh/dbinl data that has been read prior to the faulty cycle can in some cases be found here. ir holds the current instruction being executed. irc holds either the present instruction being executed or the prefetched instruction. handbook, 4 columns short stack format format (4 bits) vector number long stack format sr pch pcl ssw mm internal information internal information tpdh tpfl dbinh dbinl internal information ir irc tpfh tpdl sp mcd512
august 1993 15 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 5.5.2 t he s pecial s tatus w ord (ssw) fig.8 special status word. handbook, full pagewidth 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit fc 1 rr * if df rm hb by rw hw lc *** fc 0 fc 2 mcd513 table 4 description of ssw. table 5 internal function codes. symbol bit function rr ssw.15 rerun. by default this bit is a logic 0. if set to a logic 1, the cpu will not re-run the faulty bus cycle on return from exception (rte). - ssw.14 unde?ned, reserved if ssw.13 the faulty cycle was an instruction fetch. df ssw.12 the faulty cycle was a data fetch. rm ssw.11 the error occurred during a read-modify-write cycle. hb ssw.10 high byte by ssw.9 the faulty cycle was a byte transfer. rw ssw.8 read/write cycle hw ssw.7 high word lc ssw.6 the faulty cycle was during a long-word access. - ssw.5 unde?ned, reserved - ssw.4 unde?ned, reserved - ssw.3 unde?ned, reserved fc2 fc1 fc0 ssw.2 ssw.1 ssw.0 function code. these three bits hold the internal function code during the faulty bus cycle. the function codes are the same as for the 68000 and affect the status of the cpu during the faulty bus cycle. see table 5. fc2 fc1 fc0 address space 0 0 0 reserved 0 0 1 user data 0 1 0 user program 0 1 1 reserved 1 0 0 reserved 1 0 1 supervisor data 1 1 0 supervisor program 1 1 1 interrupt acknowledge
august 1993 16 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 fig.9 vector number and format code. vector number format code 0 0 0 0 format code either 0000 or 1111 information stacked short format (4 words) 68070 format (17 words) 1514131211109876543210 bit mcd514 5.6 cpu interrupt processing an interrupt controller handles all interrupts, solves any priority problems and passes the highest level interrupt to the cpu. the general interrupt handling mechanism and the interrupt controller are described in section 6.2. the cpu interrupt handling follows the same basic rules as in the 68000. however, the following changes have been made to simplify system development: interrupts with a priority level equal to or less than the priority level actually running will not be accepted. during the acknowledge cycle of an interrupt, the ipl bits of the status register are set to the priority level of the acknowledged interrupt. an exception to this is when the im bit in syscon2 is a logic 0. in this case level 7 is loaded into the status register. see section 6.1.2. if the priority of the interrupt pending is greater than the current processor priority then: the exception processing sequence is started. a copy of the status register is saved. the privilege level is set to supervisor state. tracing is suppressed. the priority level of the processor is set to that of the interrupt being acknowledged. the processor then gets the vector number from the interrupting device, classifies it as an interrupt acknowledge, and displays the interrupt level number being acknowledged on the address bus. if autovectoring is requested by the interrupting device, the processor internally generates a vector number that corresponds to the interrupt level number. the processor then starts normal exception processing by saving the format word, program counter, and status register in the supervisor stack. the value of the vector in the format word is either supplied externally by the requesting device or is an internally generated vector number multiplied by four (format is all zeros). the program counter value is the address of the instruction that would have been executed if the interrupt had not been present. then the interrupt vector contents are fetched and loaded into the program counter. the interrupt handling routine starts with normal instruction execution. priority level 7 is a special case; it can only be detected if the priority level was set to a lower value in between.
august 1993 17 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 6 system control 6.1 memory mapping the p90ce201 accesses the external rom and ram via 8 data lines and up to 24 address lines. data access to or from the memories is bytewise. the data will be split or restructured internally to match the internal 16-bit data format. the upper byte (bits 15 to 8) of the data is taken from the even address, the lower byte (bits 7 to 0) from the odd address (msb address + 1). for external memory control the device provides the r/wn signal together with chip enable signals for rom (csromn) and ram (csramn). csromn is activated in the internal address range 0h to ffffffh. the csramn signal is activated in the internal address range 1000000h to 1ffffffh. in the external world ram and rom are wired in parallel with a maximum address range of 16 mbytes each. if the larger memory of ram or rom is smaller than 16 mbytes the unused address pins can be used as port pins. the advantages of this addressing scheme are: maximum flexibility for ram and rom sizes. the full physical memory size can be used without any restrictions. the minimum number of address pins are used. the validity of data is signalled to the cpu by the internal signal dtackn. this signal is generated internally after a programmable delay (wait states). by programming the number of wait cycles the user can adapt the program execution times to his memory access times. after reset the delay for the dtackn signal is set to its maximum value. programming the number of wait cycles is described in section 6.3.2. fig.10 external memory interface timing - word access. handbook, full pagewidth mlb004 phi1 a0 a23 d0 d7 csrxmn r/wn (additional wait states) s0 s1 s2 s3 sb sb s4 s5 s0 s1 s2 s3 sb sb s4 s5 s0 s1 byte read byte write
august 1993 18 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 fig.11 external memory interface timing - byte access. handbook, full pagewidth mlb005 phi1 a0 a23 d0 d7 csrxmn r/wn (additional wait states) s0 s1 s2 s3 sb sb s4 s5 s0 s1 s2 s3 sb sb s4 s5 s0 s1 byte read byte write
august 1993 19 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 6.2 interrupt controller an interrupt controller handles all internal and external interrupts. it passes the interrupt with the highest level priority to the cpu. the following interrupt requests are generated by the on-chip peripherals. i 2 c1 i 2 c2 uart receiver uart transmitter timer 2 timer 1 timer 0. the following interrupt requests are sent via external pins. intn0 to intn7 6.2.1 i nterrupt arbitration the priority level of all interrupts are programmable and each may be allocated a value between 0 and 7. level 7 has the highest priority, level 0 disables the corresponding interrupt source. in the event of interrupt requests of equal priority level occurring at the same time, then a hardware mechanism gives the following order. intn7 intn6 intn5 intn4 intn3 intn2 intn1 intn0 timer 2 timer 1 timer 0 uart receiver uart transmitter i 2 c2 i 2 c1. the execution of interrupt routines may be interrupted by another higher priority level interrupt request (nested interrupts). in the 68070 mode (syscon2.7 = 1), when an interrupt is serviced by the cpu, the corresponding level is loaded into the status register. this prevents the current interrupt from getting interrupted by another interrupt request with the same or lower priority level. if syscon2.7 = 0, priority level 7 will always be loaded into the status register and therefore the current interrupt cannot be interrupted by any other interrupt request. 6.2.2 a cknowledge and interrupt vectors when the cpu is ready to service a particular interrupt request, it initiates an interrupt acknowledge cycle in order to obtain the interrupt vector from the requesting device. when the device recognizes that its interrupt request has been accepted it either provides an 8-bit interrupt vector together with an internal dtackn signal (vector mode), or it asserts an internal avn signal and the interrupt vector is calculated from the interrupt level. 6.2.3 e xternal latched interrupts intn7 to intn0 are 8 external interrupt inputs; each triggered on the falling edge of the input. their priority levels as well as their interrupt vectors are programmable. as an alternative function intn7 to intn0 may be used as i/o ports. when an interrupt pin is programmed as a port, the corresponding bit in the port control register lpcrh (or lpcrl) is used for port i/o. a read from either of these two registers reads the value from the corresponding bit in the port control register. a read from the port pad control register lpph (or lppl) reads the value from the corresponding port input pin. a write to lpcrh (or lpcrl) or to lpph (or lppl) writes the value to the corresponding port register, from where it is driven to the corresponding port pin. the port function is configured as a quasi-bidirectional port. a bit is set to input mode by writing a logic 1 to the corresponding port control register bit. this drives a weak logic 1 to the corresponding output pin, which can be overwritten by an external signal. in the following register descriptions n represents the external interrupt number (0 to 7), its associated registers are identified using the same number.
august 1993 20 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 6.2.4 l atched i nterrupt r egister n (lirn) table 6 description of lirn bits. table 7 interrupt intnn control. table 8 selection of interrupt priority level. symbol bit function intnc1 intnc0 lirn.7 lirn.6 interrupt control. these two bits enable/disable the external interrupt intnn, or select the pin as an i/o port. see table 7. avn lirn.5 autovector. when avn = 0; intnn is an autovectored interrupt and the processor calculates the appropriate vector from a ?xed vector table. this is also the default value. when avn = 1; intnn is a vectored interrupt and the peripheral must provide an 8-bit vector number. - lirn.4 not used; reserved pir lirn.3 pending interrupt request. if pir = 1; then a valid interrupt request has been detected. it is automatically reset by the interrupt acknowledge cycle from the cpu. if pir = 0; there is no pending interrupt request; this is also the default value. pir can be set or reset by software by writing a logic 1 or logic 0 respectively to pirn. ipl2 ipl1 ipl0 lirn.2 lirn.1 lirn.0 interrupt priority level. these three bits select the interrupt priority level for the external interrupt intnn. see table 8. intnc1 intnc0 interrupt control 0 0 interrupt disabled; this is also the default value. 0 1 interrupt enabled 1 0 interrupt pin is selected as an i/o port. 1 1 reserved ipl2 ipl1 ipl0 priority level 0 0 0 interrupt inhibited; this is also the default value. 0 0 1 level 1 0 1 0 level 2 0 1 1 level 3 1 0 0 level 4 1 0 1 level 5 1 1 0 level 6 1 1 1 level 7 fig.12 latched interrupt register n (lirn). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intnc1 intnc0 avn - pir ipl2 ipl1 ipl0
august 1993 21 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 6.2.5 l atched i nterrupt v ector n (livn) fig.13 latched interrupt vector n (livn). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iv.7 iv.6 iv.5 iv.4 iv.3 iv.2 iv.1 iv.0 table 9 description of livn bits. 6.2.6 l atched p ort c ontrol r egister h igh (lpcrh) symbol bit function iv.7 to iv.0 livn.7 to livn.0 8-bit interrupt vector number. the default value of this register is 0fh. fig.14 latched port control register high (lpcrh). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intn7 - intn6 - intn5 - intn4 - 6.2.7 l atched p ort c ontrol r egister l ow (lpcrl) fig.15 latched port control register low (lpcrl). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intn3 - intn2 - intn1 - intn0 -
august 1993 22 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 6.2.8 l atched p ort p in r egister h igh (lpph) 6.2.9 l atched p ort p in r egister l ow (lppl) fig.16 latched port pin register high (lpph). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intn7 - intn6 - intn5 - intn4 - fig.17 latched port pin register low (lppl). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intn3 - intn2 - intn1 - intn0 -
august 1993 23 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 6.3 system control registers the p90ce201 has two system control registers syscon1 and syscon2 which allow system parameters to be selected. 6.3.1 s ystem c ontrol r egister 1 (syscon1) table 10 description of syscon1 bits. table 11 selection of memory access times for rom and ram areas. notes 1. 1 internal clock cycle contains 2 wait states. 2. all other states are undefined and reserved. symbol bit function - syscon1.15 to syscon1.8 these eight bits are not used. nrod2 nrod1 nrod0 syscon1.7 syscon1.6 syscon1.5 these three bits select the access time for the rom area. after a reset operation these bits are logic 0s. see table 11. - syscon1.4 not used - syscon1.3 not used nrad2 nrad1 nrad0 syscon1.2 syscon1.1 syscon1.0 these three bits select the access time for the ram area. after a reset operation these bits are logic 0s. see table 11 nrod2 nrod1 nrod0 add wait states f xtal (mhz) unit nrad2 nrad1 nrad0 24 20 16 12 0 0 0 8 185 235 310 435 ns 0 0 1 4 101 135 185 268 ns 0 1 0 2 60 85 122 185 ns 0 1 1 0 18 35 60 101 ns fig.18 system control register 1 (syscon1). handbook, full pagewidth 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit nrad1 nrod2 nrod1 nrod0 nrad0 nrad2 mlb011
august 1993 24 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 6.3.2 s ystem c ontrol r egister 2 (syscon2) fig.19 system control register 2 (syscon2). handbook, full pagewidth 0 t1 ps t1 po mlb012 1 toed 0 2 54 3 876 im wd 9 15 14 13 12 11 10 bit i c2 con 2 i c1 con 2 t2 sel psbpclk 1 psbpclk 0 to ps toed 1 i c1 po 2 table 12 description of syscon2 bits. symbol bit function - syscon2.15 to syscon2.13 these three bits are not used. i 2 c2con syscon2.12 this bit along with the three bits cr0, cr1 and cr2 held in the serial control register (s2con), are used to select the bitrate of the i 2 c-bus 2 interface. if i 2 c2con = 0; the interface operates with a high bitrate. if i 2 c2con = 1; the interface operates with a low bitrate. i 2 c1con syscon2.11 this bit along with the three bits cr0, cr1 and cr2 held in the serial control register (s1con), are used to select the bitrate of the i 2 c-bus 1 interface. if i 2 c1con = 0; the interface operates with a high bitrate. if i 2 c1con = 1; the interface operates with a low bitrate. t2sel syscon2.10 this bit selects the frequency of the clock for timer 2. if t2sel = 0; the timer operates at a frequency of f xtal /2. if t2sel = 1; the timer operates at a frequency of bpclk/4. psbpclk1 psbpclk0 syscon2.9 syscon2.8 these two bits control the prescaler for the basic peripheral clock. see table 13. im syscon2.7 if im = 0; level 7 is loaded into the status register during interrupt processing to prevent the cpu from being interrupted by another interrupt source. if im = 1; the current interrupt level is loaded into the status register allowing nested interrupts. wd syscon2.6 this bit enables or disables the watchdog timer for bus error (internal) detection. if wd = 0; the timer is disabled. if wd = 1; the timer is enabled for bus error detection. if no acknowledge has been sent by the addressed device after 128 16 internal clock cycles the on-chip bus error signal is activated. i 2 c1po syscon2.5 the state of this bit determines whether general port pins gp.7/sda1 and gp.6/scl1 are used as port pins or in their i 2 c-bus function. when i 2 c1p0 = 0; the port function is selected. when i 2 c1p0 = 1; the i 2 c-bus is selected. t0ps syscon2.4 this bit enables or disables the prescaler for timer 0. if t0ps = 0; the prescaler is disabled and the timer operates at a frequency of f xtal /2. if t0ps = 1; the prescaler is enabled and the timer operates at a frequency of f xtal /32. t0ed1 t0ed0 syscon2.3 syscon2.2 these two bits select which transition at the external input will trigger an increment of timer 0. see table 14.
august 1993 25 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 note 1. all bits of this register have a default value of logic 0 except toed1 which has a default value of logic 1. table 13 selection of basic peripheral clock for bpclk = 4 mhz. table 14 selection of input trigger for t0. t1ps syscon2.1 this bit enables or disables the prescaler for timer 1. if t1ps = 0; the prescaler is disabled and the timer operates at a frequency of f xtal /2. if t1ps = 1; the prescaler is enabled and the timer operates at a frequency of f xtal /32. t1po syscon2.0 this bit selects whether bit 5 of the general purpose port acts as a port or as an input to timer 1. if t1po = 0; bit 5 of the general purpose port acts as a port. if t1po = 1; bit 5 of the general purpose port acts as an input to timer 1. psbpclk1 psbpclk0 divisor f xtal (mhz) 0 0 3.0 24 0 1 2.5 20 1 0 2.0 16 1 1 1.5 12 toed1 toed0 transition 0 0 edge detection disabled 0 1 low-to-high transitions will be monitored. 1 0 high-to-low transitions will be monitored. this is the default value after a reset operation. 1 1 any transition will be monitored. symbol bit function
august 1993 26 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 6.4 reset the reset input for the p90ce201 is reset (pin 53). a schmitt trigger is used at the input for noise rejection. the output of the schmitt trigger is sampled by the reset circuitry every machine cycle. the internal reset circuitry has an additional input which is activated by an overflow of the watchdog timer (wdtim). the on-chip reset configuration is shown in fig.20. a global reset may be performed by three different methods: applying an external signal to the reset pin automatic power-on-reset circuitry activated by an overflow of the watchdog timer. during the reset operation the cpu and peripherals are reset. after an internal start-up time, the cpu reads the reset vectors (the reset vectors are four words long). address 000000h is loaded into the supervisor stack pointer (ssp), and address 000004h is loaded into the program counter (pc). as soon as the ssp and pc have been loaded, the cpu initializes the status register to interrupt level 7. instruction execution then starts at the address indicated by the program counter. 6.4.1 e xternal reset using the reset pin an external reset is accomplished by applying an external signal to the reset pin. to ensure that the oscillator is stable before the controller starts, the external signal must be held high for at least 100 ms. 6.4.2 a utomatic p ower - on reset providing the rise time of v dd does not exceed 10 ms, an automatic reset can be obtained by connecting the reset pin to v dd , via a 2.2 m f capacitor. when the power is switched on, the voltage on the reset pin is equal to v dd minus the capacitor voltage, and decreases from v dd as the capacitor charges through the internal resistor (r reset ) to ground. the larger the capacitor, the more slowly v reset decreases. v reset must remain above the lower threshold of the schmitt trigger long enough to effect a complete reset. the time required is the oscillator start-up time, plus 2 machine cycles. the power-on reset circuitry is shown in fig.21. 6.4.3 r eset activated by an overflow of the w atchdog t imer a reset can also be initiated by an overflow of the watchdog timer (see fig.20). after a reset operation the watchdog timer is disabled. note that when the cpu executes a reset instruction, the cpu is not affected, only the on-chip peripherals are reset. fig.20 on-chip reset configuration. mlb007 schmitt trigger reset circuitry reset on-chip resistor watchdog timer overflow fig.21 power-on reset circuitry. handbook, halfpage v dd v dd reset 2.2 m f r reset mlb006 p90ce201
august 1993 27 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 6.5 clock circuitry the oscillator circuit of the p90ce201 is a single-stage inverting amplifier in a pierce oscillator configuration. the circuitry between xtal1 and xtal2 is basically an inverter biased to the transfer point. either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuitry. both are operated in parallel resonance. xtal1 is the high gain amplifier input, and xtal2 is the input; see fig.22. to drive the p90ce201 externally, xtal1 is driven from an external source and xtal2 left open-circuit; see fig.23. the p90ce201 is specified for a maximum crystal frequency of 24 mhz. the internal clock frequency is the crystal frequency (f xtal ) divided by 2. for some peripherals such as the uart and watchdog timer, a main prescaler generates a basic peripheral clock. frequencies other than the basic peripheral clock will be generated within the peripherals. the prescaler is programmed by register syscon2. table 15 shows the frequencies of the basic peripheral clock generated by the main prescaler. table 15 basic peripheral clock frequencies. f xtal (mhz) f int (mhz) f int divisor (mhz) 3 2.5 2 1.5 24 12 4.00 4.80 6.00 8.00 20 10 3.33 4.00 5.00 6.66 16 8 2.66 3.20 4.00 5.33 12 6 2.00 2.40 3.00 4.00 fig.22 oscillator circuit. handbook, halfpage c1 xtal1 xtal2 20 pf c2 mla763 20 pf fig.23 driving from an external source. handbook, halfpage xtal1 xtal2 mla764 external clock (not ttl compatible) not connected
august 1993 28 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 7 instruction set the p90ce201 is completely code compatible with the 68000. consequently, programs developed for the 68000 will run on the p90ce201. this applies to both the source and object codes. the instruction set was designed to minimize the number of mnemonics that the programmer has to remember. mnemonic description operation condition codes xnzvc abcd add decimal with extend (destination) 10 + (source) 10 +x ? destination * u * u * add add binary (destination) + (source) ? destination ***** adda add address (destination) + (source) ? destination ----- addi add immediate (destination) + immediate data ? destination ***** addq add quick (destination) + immediate data ? destination ***** addx add extended (destination) + (source) + x ? destination ***** and and logical (destination) l (source) ? destination - **00 andi and immediate (destination) l immediate data ? destination - **00 asl, asr arithmetic shift (destination) shifted by < count > ? destination ***** b cc branch conditionally if cc then pc + d ? pc ----- bchg test a bit and change ~(< bit number >) of destination ? z ~(< bit number >) of destination ? < bit number > of destination -- * -- bclr test a bit and clear ~(< bit number >) of destination ? z -- * -- bra branch always pc + d ? pc ----- bset test a bit and set ~(< bit number >) of destination ? z 1 ? < bit number > of destination -- * -- bsr branch to subroutine pc ? sp @ - ; pc + d ? pc ----- btst test a bit ~(< bit number >) of destination ? z -- * -- chk check register against bounds if dn < 0 or dn > (< source >) then trap - * uuu clr clear an operand 0 ? destination - 0100 cmp compare (destination) - (source) - **** cmpa compare address (destination) - (source) - **** cmpi compare immediate (destination) - immediate data - **** cmpm compare memory (destination) - (source) - **** db cc test condition, decrement & branch if (not cc) then dn - 1 ? dn; if dn 1- 1 then pc + d ? pc ----- divs signed divide (destination) / (source) ? destination - ***0 divu unsigned divide (destination) / (source) ? destination - ***0
august 1993 29 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 eor exclusive or logical (destination) ? (source) ? destination - **00 eori exclusive or immediate (destination) ? immediate data ? destination - **00 exg exchange register rx ? ry ----- ext sign extend (destination) sign - extended ? destination - **00 jmp jump destination ? pc ----- jsr jump to subroutine pc ? sp @ - ; destination ? pc ----- lea load effective address destination ? an ----- link link and allocate an ? sp @ - ; sp ? an; sp + d ? sp ----- lsl, lsr logical shift (destination) shifted by < count > ? destination * * * 0 * move move data from source to destination (source) ? destination - **00 move to ccr move to condition code (source) ? ccr ***** move to sr move to the status register (source) ? sr ***** move from sr move from the status register sr ? destination ----- move usp move user stack pointer usp ? an; an ? usp ----- movea move address (source) ? destination ----- movem move multiple registers registers ? destination; (source) ? registers ----- movep move peripheral data (source) ? destination ----- moveq move quick immediate data ? destination - **00 muls signed multiply (destination) * (source) ? destination - ***0 mulu unsigned multiply (destination) * (source) ? destination - ***0 nbcd negate decimal with extend 0 - (destination) 10 - x ? destination * u * u * neg negate 0 - (destination) ? destination ***** negx negate with extend 0 - (destination) - x ? destination ***** nop no operation - ----- mnemonic description operation condition codes xnzvc
august 1993 30 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 notes 1. [ ] = bit number 2. * = affected 3. - = unaffected 4. 0 = cleared 5. 1 = set 6. u = defined 7. @ = location addressed by not logical complement ~(destination) ? destination - **00 or inclusive or logical (destination) v (source) ? destination - **00 ori inclusive or immediate (destination) v immediate data ? destination - **00 pea push effective address destination ? sp @ - ----- reset reset external devices - ----- rol, ror rotate (without extend) (destination) rotated by < count > ? destination - **0* roxl, roxr rotate with extend (destination) rotated by < count > ? destination * * * 0 * rte return from exception sp @ +? sr; sp @ +? pc ***** rtr return and restore condition codes sp @ +? sr; sp @ +? pc ***** rts return from subroutine sp @ +? pc ----- sbcd subtract decimal with extend (destination) 10 - (source) 10 - x ? destination * u * u * s cc set according to condition if cc then 1 ? destination; else 0 ? destination ----- stop load status register and stop immediate data ? sr; stop ***** sub subtract binary (destination) - (source) ? destination ***** suba subtract address (destination) - (source) ? destination ----- subi subtract immediate (destination) - immediate data ? destination ***** subq subtract quick (destination) - immediate data ? destination ***** subx subtract with extend (destination) - (source) - x ? destination ***** swap swap register halves register [ 31:16 ] ? register [ 15:0 ] - **00 tas test and set an operand (destination) tested ? cc; 1 ? [ 7 ] of destination - **00 trap trap pc ? ssp @ - ; sr ? ssp @ - ; (vector) ? pc ----- trapv trap on over?ow if v then trap ----- tst test and operand (destination) tested ? cc - **00 unlk unlink an ? sp; sp @ +? an ----- mnemonic description operation condition codes xnzvc
august 1993 31 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 7.1 addressing modes table 16 data addressing modes. notes 1. ea = effective address 2. an = address register 3. dn = data register 4. xn = address or data register used as index register 5. n = 1 for bytes; 2 for words; 4 for long words 6. ? = replaces 7. sr = status register 8. pc = program counter 9. () = contents of 10. d 8 = 8-bit offset (displacement) 11. d 16 = 16-bit offset (displacement) 12. sp = stack pointer 13. ssp = system stack pointer 14. usp = user stack pointer mode generation register direct addressing data register direct ea = dn address register direct ea = an absolute data addressing absolute short ea = (next words) absolute long ea = (next two words) program counter relative addressing relative with offset ea = (pc) + d 16 relative with index and offset ea = (pc) + (xn) + d 8 register indirect addressing register indirect ea = (an) postincrement register indirect ea = (an), an ? an + n predecrement register indirect an ? an - n, ea = (an) register indirect with offset ea = (an) + d 16 indexed register indirect with offset ea = (an) + (xn) + d 8 immediate data addressing immediate data = next word(s) quick immediate inherent data implied addressing implied register ea = sr, usp, ssp, pc, sp
august 1993 32 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 7.2 instruction timing this data assumes that both memory read and write cycle times are four internal clock periods (no additional wait states). additional wait states for memory accesses have to be added to the total instruction time. accesses to registers listed in the register map are only three clock periods, therefore one clock period can be subtracted for each access to such a register. however, access to the uart registers takes up to ten clock periods due to synchronization. consequently, ten clock periods have to be added for uart register accesses. table 17 effective address calculation times. note 1. the number of bus read and write cycles are shown in parentheses as (r/w). table 18 move byte and move word instruction clock periods. source addressing mode byte, word long rn data address register direct 0 (0/0) 0 (0/0) (an) address register indirect 4 (1/0) 8 (2/0) (an) + address register indirect postincrement 4 (1/0) 8 (2/0) - (an) address register indirect predecrement 7 (1/0) 11 (2/0) d(an) address register indirect displacement 11 (2/0) 15 (3/0) d(an, xi) address register indirect with index 14 (2/0) 18 (3/0) xxx.s absolute short 8 (2/0) 12 (3/0) xxx.l absolute long 12 (3/0) 16 (4/0) d(pc) program counter with displacement 11 (2/0) 15 (3/0) d(pc, xi) program counter with index 14 (2/0) 18 (3/0) #xxx immediate 4 (1/0) 8 (2/0) source rn (an) (an) +- (an) d(an) d(an,xi) xxx.s xxx.l rn 7 (1/0) 11 (1/1) 11 (1/1) 14 (1/1) 18 (1/1) 21 (1/1) 15 (1/1) 19 (1/1) (an) 11 (2/0) 15 (2/1) 15 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 19 (2/1) 23 (2/1) (an) + 11 (2/0) 15 (2/1) 15 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 19 (2/1) 23 (2/1) - (an) 14 (2/0) 18 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 28 (2/1) 22 (2/1) 26 (2/1) d(an) 18 (3/0) 22 (3/1) 22 (3/1) 25 (3/1) 29 (3/1) 32 (3/1) 26 (3/1) 30 (3/1) d(an,xi) 21 (3/0) 25 (3/1) 25 (3/1) 28 (3/1) 32 (3/1) 35 (3/1) 29 (3/1) 33 (3/1) xxx.s 15 (3/0) 19 (3/1) 19 (3/1) 22 (3/1) 26 (3/1) 29 (3/1) 23 (3/1) 27 (3/1) xxx.l 19 (4/0) 23 (4/1) 23 (4/1) 26 (4/1) 30 (4/1) 33 (4/1) 27 (4/1) 31 (4/1) d(pc) 18 (3/0) 22 (3/1) 22 (3/1) 25 (3/1) 29 (3/1) 32 (3/1) 26 (3/1) 30 (3/1) d(pc,xi) 21 (3/0) 25 (3/1) 25 (3/1) 28 (3/1) 32 (3/1) 35 (3/1) 29 (3/1) 33 (3/1) #xxx 11 (2/0) 15 (2/1) 15 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 19 (2/1) 23 (2/1)
august 1993 33 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 19 move long instruction clock periods. table 20 standard instruction clock periods. notes 1. + = add effective address calculation time 2. * = the duration of the instruction is constant 3. ** = indicates maximum value. source rn (an) (an) +- (an) d(an) d(an,xi) xxx.s xxx.l rn 7 (1/0) 15 (1/2) 15 (1/2) 18 (1/2) 22 (2/2) 25 (2/2) 19 (2/2) 23 (3/2) (an) 15 (3/0) 23 (3/2) 23 (3/2) 26 (3/2) 30 (4/2) 33 (4/2) 27 (4/2) 31 (5/2) (an) + 15 (3/0) 23 (3/2) 23 (3/2) 26 (3/2) 30 (4/2) 33 (4/2) 27 (4/2) 31 (5/2) - (an) 18 (3/0) 26 (3/2) 26 (3/2) 29 (3/2) 33 (4/2) 36 (4/2) 30 (4/2) 34 (5/2) d(an) 22 (4/0) 30 (4/2) 30 (4/2) 33 (4/2) 37 (5/2) 40 (5/2) 34 (5/2) 38 (6/2) d(an,xi) 25 (4/0) 33 (4/2) 33 (4/2) 36 (4/2) 40 (5/2) 43 (5/2) 37 (5/2) 41 (6/2) xxx.s 19 (4/0) 27 (4/2) 27 (4/2) 30 (4/2) 34 (5/2) 37 (5/2) 31 (5/2) 35 (6/2) xxx.l 23 (5/0) 31 (5/2) 31 (5/2) 34 (5/2) 38 (6/2) 41 (6/2) 35 (6/2) 39 (7/2) d(pc) 22 (4/0) 30 (4/2) 30 (4/2) 33 (4/2) 37 (5/2) 40 (5/2) 34 (5/2) 38 (6/2) d(pc,xi) 25 (4/0) 33 (4/2) 33 (4/2) 36 (4/2) 40 (5/2) 43 (5/2) 37 (5/2) 41 (6/2) #xxx 15 (3/0) 23 (3/2) 23 (3/2) 26 (3/2) 30 (4/2) 33 (4/2) 27 (4/2) 31 (5/2) instr size op < ea > ,an op < ea > ,dn op < dn > ,m add byte, word 7 + (1/0) 7 + (1/0) 11 + (1/1) long 7 + (1/0) 7 + (1/0) 15 + (1/2) and byte, word - 7 + (1/0) 11 + (1/1) long - 7 + (1/0) 15 + (1/2) cmp byte, word 7 + (1/0) 7 + (1/0) - long 7 + (1/0) 7 + (1/0) - divs -- 169 + ** (1/0) (3) - divu -- 130 + * (1/0) (2) - eor byte, word - 7 + (1/0) 11 + (1/1) long - 7 + (1/0) 15 + (1/2) muls -- 76 + * (1/0) (2) - mulu -- 76 + * (1/0) (2) or byte, word - 7 + (1/0) 11 + (1/1) long - 7 + (1/0) 15 + (1/2) sub byte, word 7 + (1/0) 7 + (1/0) 11 + (1/1) long 7 + (1/0) 7 + (1/0) 15 + (1/2)
august 1993 34 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 21 immediate instruction clock periods. note 1. + = add effective calculation time. instr. size op < # > ,dn op < # > ,an op < # > ,< m > addi byte, word 14 (2/0) - 18 + (2/1) long 18 (3/0) - 26 + (3/2) addq byte, word 7 (1/0) 7 (1/0) 11 + (1/1) long 7 (1/0) 7 (1/0) 15 + (1/2) andi byte, word 14 (2/0) - 18 + (2/1) long 18 (3/0) - 24 + (3/2) cmpi byte, word 14 (2/0) - 14 + (2/0) long 18 (3/0) - 18 + (3/0) eori byte, word 14 (2/0) - 18 + (2/1) long 18 (3/0) - 26 + (3/2) moveq long 7 (1/0) -- ori byte, word 14 (2/0) - 18 + (2/1) long 18 (3/0) - 26 + (3/2) subi byte, word 14 (2/0) - 18 + (2/1) long 18 (3/0) - 26 + (3/2) subq byte, word 7 (1/0) 7 (1/0) 11 + (1/1) long 7 (1/0) 7 (1/0) 15 + (1/2)
august 1993 35 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 22 single operand instruction clock periods. notes 1. + = add effective calculation time 2. * = subtract one read cycle ( - 4(1/0)) from effective address calculation 3. ** = subtract two read cycles ( - 8(2/0)) from effective address calculation. table 23 shift/rotate instruction clock periods. note 1. + = add effective calculation time. instruction size register memory clr byte, word 7 (1/0) 11 (1/1) + * (2) long 7 (1/0) 15 (1/2) + ** (3) nbcd byte 10 (1/0) 14 (1/1) (2) neg byte, word 7 (1/0) 11 (1/1) + long 7 (1/0) 15 (1/2) + negx byte, word 7 (1/0) 11 (1/1) + long 7 (1/0) 15 (1/2) + not byte, word 7 (1/0) 11 (1/1) + long 7 (1/0) 15 (1/2) + scc byte, word 13 (1/0) 17 (1/1) + long 13 (1/0) 14 (1/1) + tas byte, word 10 (1/0) 15 (2/1) + * (2) tst byte, word 7 (1/0) 7 (1/0) + long 7 (1/0) 7 (1/0) + instruction size register memory asr,asl byte, word 13 + 3n (1/0) 14 (1/1) + long 13 + 3n (1/0) - lsr,lsl byte, word 13 + 3n (1/0) 14 (1/1) + long 13 + 3n (1/0) - ror,rol byte, word 13 + 3n (1/0) 14 (1/1) + long 13 + 3n (1/0) - roxr,roxl byte, word 13 + 3n (1/0) 14 (1/1) + long 13 + 3n (1/0) -
august 1993 36 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 24 bit manipulation instruction clock periods. note 1. + = add effective calculation time. table 25 conditional instruction clock periods. note 1. + = add effective calculation time. instruction size dynamic static register memory register memory bchg byte - 14 (1/1) +- 21 (2/1) + long 10 (1/0) - 17 (2/0) - bclr byte - 14 (1/1) +- 21 (2/1) + long 10 (1/0) - 17 (2/0) - bset byte - 14 (1/1) +- 21 (2/1) + long 10 (1/0) - 17 (2/0) - btst byte - 7 (1/0) +- 14 (2/0) + long 7 (1/0) - 14 (2/0) - instruction displacement trap/branch taken trap/branch not taken bcc .b 13 (1/0) 13 (1/0) .w 14 (2/0) 14 (2/0) bra .b 13 (1/0) - .w 14 (2/0) - bsr .b 21 (1/2) - .w 25 (2/2) - dbcc cc true - 14 (2/0) cc false 17 (2/0) 17 (3/2) chk - 70 (3/4) 19 (1/0) + trapv - 55 (3/4) 10 (1/0)
august 1993 37 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 26 jmp, jsr, lea, pea, movem instruction clock periods. note 1. n = number of registers to move. table 27 multi-precision instruction clock periods. instr size (an) (an) +- (an) d(an) d(an, xi) xxx.s xxx.l d(pc) d(pc,xi) jmp - 7 -- 14 17 14 18 14 17 - (1/0) -- (2/0) (2/0) (2/0) (3/0) (2/0) (2/0) jsr - 18 -- 25 28 25 29 25 28 - (1/2) -- (2/2) (2/2) (2/2) (3/2) (2/2) (2/2) lea - 7 -- 14 17 14 18 14 17 - (1/0) -- (2/0) (2/0) (2/0) (3/0) (2/0) (2/0) pea - 18 -- 25 28 25 29 25 28 - (1/2) -- (2/2) (2/2) (2/2) (3/2) (2/2) (2/2) movem m ? r .w 26 + 7n (2 + n/0) 26 + 7n (2 + n/0) - - 30 + 7n (3 + n/0) 33 + 7n (3 + n/0) 30 + 7n (3 + n/0) 34 + 7n (4 + n/0) 30 + 7n (3 + n/0) 33 + 7n (3 + n/0) .l 26 + 11n (2 + 2n/0) 26 + 11n (2 + 2n/0) - 30 + 11n (3 + 2n/0) 33 + 11n (3 + 2n/0) 30 + 11n (3 + 2n/0) 34 + 11n (4 + 2n/0) 30 + 11n (3 + 2n/0) 33 + 11n (3 + 2n/0) movem r ? m .w 23 + 7n (2/n) - - 23 + 7n (2/n) 27 + 7n (3/n) 30 + 7n (3/n) 27 + 7n (3/n) 31 + 7n (4/n) - - - - .l 23 + 11n (2/2n) - - 23 + 11n (2/2n) 27 + 11n (3/2n) 30 + 11n (3/2n) 27 + 11n (3/2n) 31 + 11n (4/2n) - - - - instruction size op dn, dn op m, m addx byte, word 7 (1/0) 28 (3/1) long 7 (1/0) 40 (5/2) cmpm byte, word - 18 (3/0) long - 26 (5/0) subx byte, word 7 (1/0) 28 (3/1) long 7 (1/0) 40 (5/2) abcd byte 10 (1/0) 31 (3/1) sbcd byte 10 (1/0) 31 (3/1)
august 1993 38 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 28 miscellaneous clock periods. note 1. + = add effective address calculation time. instruction size register memory register to memory memory to register andi to ccr - 14 (2/0) --- andi to sr - 14 (2/0) --- eori to ccr - 14 (2/0) --- eori to sr - 14 (2/0) --- exg - 13 (1/0) --- ext word 7 (1/0) --- long 7 (1/0) --- link - 25 (2/2) --- move from sr - 7 (1/0) 11 (1/1) +- - move to ccr - 10 (1/0) 10 (1/0) +- - move to sr - 10 (1/0) 10 (1/0) +- - move from usp - 7 (1/0) --- move to usp - 7 (1/0) --- movep word --- 25 (2/2) 22 (4/0) long --- 39 (2/4) 36 (6/0) nop - 7 (1/0) --- ori to ccr - 14 (2/0) --- ori to sr - 14 (2/0) --- reset - 154 (1/0) --- rte - short format - 39 (5/0) --- rte - long format ---- no rerun - 140 (18/0) --- with rerun - 146 (18/0) --- return of tas - 151 (19/0) --- rtr - 22 (4/0) --- rts - 15 (3/0) --- stop - 17 (2/0) --- swap - 7 (1/0) --- unlk - 15 (3/0) ---
august 1993 39 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 29 exception processing clock periods. note 1. the interrupt acknowledge bus cycle is assumed to take four clock periods. 2. the maximum time from when reset is first sampled as released to first instruction fetch. exception number of clock periods address error 158 (3/17) interrupt 65 (4/4), note 1 illegal instruction 55 (3/4) privilege instruction 55 (3/4) trace 55 (3/4) trap 52 (3/4) divide by zero 64 (3/4) + reset (note 2) 43 (4/0)
august 1993 40 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 8i 2 c-bus interface 8.1 general the p90ce201 contains two fully independent i 2 c-bus serial interfaces (i 2 c1 and i 2 c2); the functionality of both is identical. the i 2 c-bus interfaces can operate in four modes: 1. master transmitter 2. master receiver 3. slave transmitter 4. slave receiver. the i 2 c-bus interface is connected to the i 2 c-bus by a data pin (sda) and by a clock pin (scl). data transport, clock generation, address recognition and bus arbitration are all controlled by hardware. each i 2 c-bus interface is controlled by a set of six registers. fig.24 block diagram of i 2 c-bus serial interface. handbook, full pagewidth mlb252 slave address snadr gc shift register sndat sdan arbitration logic scln bus clock generator snsta internal bus 76543210 sncon 76543210
august 1993 41 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 8.2 i 2 c-bus interface registers in the following register descriptions n represents the i 2 c-bus serial interface number (1 or 2); its associated registers are identified using the same number. 8.2.1 s erial c ontrol r egister (sncon) s1con is located at address 8000 2007h; s2con is located at address 8000 2017h. these registers have a default value of 00h. table 30 description of sncon bits. symbol bit function cr2 cr1 cr0 sncon.7 sncon.1 sncon.0 clock rate. these three bits along with bit syscon2.12 (or syscon2.11) determine the serial clock frequency that is generated in the master mode of operation. the frequencies of 100 khz and 400 khz can be selected for the oscillators frequencies of 12, 16, 20 and 24 mhz, as shown in table 31. ens sncon.6 enable serial i/o. when ens = 0; the serial interface i/o is disabled and reset. when ens = 1; the serial interface is enabled. sta sncon.5 start ?ag. when this bit is set in slave mode, the hardware checks the i 2 c-bus and generates a start condition if the bus is free or after the bus becomes free. if the device operates in master mode it will generate a repeated start condition. sto sncon.4 stop ?ag. if this bit is set in the master mode a stop condition is generated. a stop condition detected on the i 2 c-bus clears this bit. the stop bit may also be set in slave mode in order to recover from an error condition. in this case no stop condition is generated to the i 2 c-bus, but the hardware releases the sda and scl lines and switches to the not selected slave receiver mode. the stop ?ag is cleared by the hardware. si sncon.3 serial interrupt flag. this flag is set, and an interrupt is generated, after any of the following events occur: - a start condition is generated in master mode - the own slave address has been received during aa = 1 - the general call address has been received while snadr.0 = 1 and aa = 1 - a data byte has been received or transmitted in master mode - a data byte has been received or transmitted as selected slave - a stop or start condition is received as selected slave receiver or transmitter. while the si flag is set, scl remains low and the serial transfer is suspended. si must be reset by software. fig.25 serial control register (sncon) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cr2 ens sta sto si aa cr1 cr0
august 1993 42 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 31 selection of i 2 c-bus bit rate. note 1. cr3 is defined by syscon2.12 (or syscon2.11). aa sncon.2 assert acknowledge. when this bit is set, an acknowledge is returned after any one of the following conditions: - own slave address is received - the general call address is received (s1adr.0 = 1) - a data byte is received, while the device is programmed to be a master receiver - a data byte is received, while the device is a selected slave receiver. when this bit is reset, no acknowledge is returned. consequently, no interrupt is requested when the own slave address or general call address is received. cr3 (note 1 ) cr2 cr1 cr0 bit rate at f clk (mhz) unit device 12 16 20 24 0 0 0 0 200 266.66 333.33 400 khz fast i 2 c-bus 0 0 0 1 240 320 400 - khz 0 0 1 0 300 400 -- khz 0 011400 -- - khz 0 1 0 0 50 66.67 83.33 100 khz standard i 2 c-bus 0 1 0 1 60 80 100 - khz 0 1 1 0 75 100 -- khz 0 111100 -- - khz 1 0 0 0 6.25 8.33 10.42 12.5 khz 1 0 0 1 7.5 10 12.5 15 khz 1 0 1 0 9.38 12.5 15.63 18.75 khz 1 0 1 1 12.5 16.67 20.83 25 khz 1 1 0 0 3.13 4.17 5.21 6.25 khz 1 1 0 1 3.75 5 6.25 7.5 khz 1 1 1 0 4.69 6.25 7.81 9.38 khz 1 1 1 1 6.25 8.33 10.42 12.5 khz symbol bit function
august 1993 43 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 8.2.2 s erial s tatus r egister (snsta) s1sta resides at address 8000 2005h; s2sta resides at address 8000 2015h. the contents of the serial status registers may be used as vectors to service routines. this optimizes the response time of the software and consequently that of the i 2 c-bus. s1sta and s2sta are read-only registers. these registers have a default value of f8h. table 32 description of snsta bits. table 33 master transmitter mode. table 34 master receiver mode. symbol bit function sc4 sc3 sc2 sc1 sc0 snsta.7 snsta.6 snsta.5 snsta.4 snsta.3 status code. these 5 bits may be read in order to determine the status of the i 2 c-bus. tables 33 to 37 show all the status codes. - - - s1sta.2 s1sta.1 s1sta.0 these three bits are held low and allow the user to use the status code directly as a vector to a service routine. s1sta value description 08h a start condition has been transmitted 10h a repeated start condition has been transmitted 18h sla and w have been transmitted, ack has been received 20h sla and w have been transmitted, ack received 28h data of sndat has been transmitted, ack received 30h data of sndat has been transmitted, ack received 38h arbitration lost in sla, r/w or data s1sta value description 08h a start condition has been transmitted 10h a repeated start condition has been transmitted 38h arbitration lost while returning ack 40h sla and r have been transmitted, ack received 48h sla and r have been transmitted, ack received 50h data has been received, ack returned 58h data has been received, ack returned fig.26 serial status register (snsta). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sc4 sc3 sc2 sc1 sc0 0 0 0
august 1993 44 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 35 slave receiver mode. table 36 slave transmitter mode. table 37 miscellaneous. a bbreviations used : s1sta value description 60h own sla and w have been received, ack returned 68h arbitration lost in sla, r/w as mst. own sla and w have been received, ack returned 70h general call has been received, ack returned 78h arbitration lost in sla, r/w as mst. general call received, ack returned 80h previously addressed with own sla. data byte received, ack returned 88h previously addressed with own sla. data byte received, ack returned 90h previously addressed with general call. data byte received, ack has been returned 98h previously addressed with general call. data byte received, ack has been returned a0h a stop condition or repeated start condition received while still addressed as slv/rec or slv/trx s1sta value description a8h own sla and r received, ack returned b0h arbitration lost in sla, r/w as mst. own sla and r received, ack returned b8h data byte has been transmitted, ack received c0h data byte has been transmitted, ack received c8h last data byte has been transmitted, ack received s1sta value description 00h bus error during mst mode or selected slv mode, due to an erroneous start or stop condition f8h no relevant information available, si not set sla: 7-bit slave address r: read bit w: write bit ack: acknowledgement (acknowledge bit = logic 0) ack: no acknowledgement (acknowledge bit = logic 1) data: 8-bit data byte to or from i 2 c-bus mst: master slv: slave trx: transmitter rec: receiver.
august 1993 45 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 8.2.3 d ata s hift r egister (sndat) s1dat is located at address 8000 2001h; s2dat is located at address 8000 2011h. these two identical registers contain the serial data to be transmitted or data that has just been received. bit 7 is transmitted or received first; i.e. dat a shifted from right to left. these registers have a default value of 00h. 8.2.4 a ddress r egister (snadr) s1adr resides at address 8000 2003h; s2adr resides at address 8000 2013h. these two identical 8-bit registers may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receiver/transmitter. the lsb (gc) is used to determine whether the general call address is recognized. these registers have a default value of 00h. table 38 description of snadr bits. symbol bit function sla6 to sla0 snadr.7 to snadr.1 own slave address gc snadr.0 when a logic 0, the general call address is not recognized. when a logic 1, the general call address is recognized fig.27 data shift register (sndat). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data.7 data.6 data.5 data.4 data.3 data.2 data.1 data.0 fig.28 address register (snadr). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sla6 sla5 sla4 sla3 sla2 sla1 sla0 gc
august 1993 46 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 8.2.5 i nterrupt registers the i 2 c-bus interface contains four registers for the control of i 2 c-bus interrupts. one pair of registers (s1ir and s1iv) provide independent control of the i 2 c1 interface interrupts; the other pair of registers (s2ir and s2iv) provide independent control of the i 2 c2 interface interrupts. in the following register descriptions n represents the i 2 c-bus interface number (1 or 2), its associated registers are identified using the same number. 8.2.6 i nterrupt r egisters (snir) these registers have a default value of xx0x0000 b . table 39 description of snir bits. table 40 selection of interrupt priority level. symbol bit function - snir.7 reserved - snir.6 reserved avn snir.5 autovector. when avn = 0; the interrupt is an autovectored interrupt and the processor calculates the appropriate vector from a ?xed vector table. avn = 0 is also the default value. when avn = 1; the interrupt is a vectored interrupt and the peripheral must provide an 8-bit vector number. - snir.4 reserved pir snir.3 pending interrupt request. this bit is set to a logic 1 when a valid interrupt request has been detected. it is automatically reset by the interrupt acknowledge cycle from the cpu. if pir = 0, there is no pending interrupt request; this is also the default value. the pir bit can also be reset by software by writing a logic 0 to this location. ipl2 ipl1 ipl0 snir.2 snir.1 snir.1 interrupt priority level. these three bits select the interrupt priority level. see table 40. ipl2 ipl1 ipl0 priority level 0 0 0 interrupt inhibited; this is also the default value. 0 0 1 level 1 0 1 0 level 2 0 1 1 level 3 1 0 0 level 4 1 0 1 level 5 1 1 0 level 6 1 1 1 level 7 fig.29 interrupt register (snir). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -- avn - pir ipl2 ipl1 ipl0
august 1993 47 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 8.2.7 i nterrupt v ector (sniv) these registers have a default value of 0fh. table 41 description of sniv bits. symbol bit function iv.7 to iv.0 sniv.7 to sniv.0 8-bit interrupt vector number. the default value of this register is 0fh. fig.30 interrupt vector (sniv). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iv.7 iv.6 iv.5 iv.4 iv.3 iv.2 iv.1 iv.0
august 1993 48 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 9 uart serial interface 9.1 general this serial port is full duplex which means that it can transmit and receive simultaneously. it is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the receive register. (however, if the first byte has not been read by the time the reception of the second byte is complete, one of the bytes will be lost). the serial port receive and transmit registers are both accessed as register sbuf. writing to sbuf loads the transmit register and reading sbuf accesses the physically separate receive register. the baud rate for receiver and transmitter can be generated by any timer using its baud rate generator output. 9.2 operating modes the serial port can operate in one of four modes: mode 0: serial data enters and exits through rxd. txd outputs the shift clock. 8 data bits are transmitted or received (lsb ?rst). the baud rate is ?xed at 1/4 the basic peripheral clock. mode 1: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb ?rst), and a stop bit (1). on receive, the stop bit is stored in rb8 in register scon. the baud rate is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. mode 2: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb ?rst), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) usually represents the parity bit. on receive, the 9th data bit is stored in rb8 in scon, while the stop bit is ignored. the baud rate is ?xed at 3/32 of the bpclk frequency. mode 3: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb ?rst), a programmable 9th data bit and a stop bit (1). mode 3 is the same as mode 2 except that the baud rate in mode 3 is variable. 9.3 uart registers 9.3.1 uart s hift r egister (sbuf) the uart shift register resides at address 8000 2021h. sbuf contains the serial data to be transmitted or data just being received. bit 0 is transmitted or received first; i.e data is shifted from left to right. fig.31 uart shift register (sbuf). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0
august 1993 49 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 9.3.2 uart c ontrol r egister (scon) the serial port control register and status register (scon) contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). scon has a default value of 00h. table 42 description of scon bits. table 43 selection of the serial port modes. symbol bit function sm0 sm1 scon.7 scon.6 these two bits are used to select the serial port mode. see table 43. sm2 scon.5 enables the multiprocessor communication feature in modes 2 and 3. in modes 2 and 3, if sm2 = 1, then ri will not be activated if the received 9th data bit (rb8) is a logic 0. in mode 1, if sm2 = 1, then ri will not be activated unless a valid stop bit was received. in mode 0, sm2 should be a logic 0. ren scon.4 enables serial reception and is set by software to enable reception, and cleared by software to disable reception. tb8 scon.3 the 9th data bit that will be transmitted in modes 2 and 3. set or cleared by software as required. rb8 scon.2 in modes 2 and 3, rb8 is the 9th data bit that is received. in mode 1, if sm2 = 0, then rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti scon.1 transmit interrupt ?ag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. must be cleared by software. ri scon.0 receive interrupt ?ag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (however see sm2). must be cleared by software. sm0 sm1 mode description baud rate 0 0 0 shift register bpclk/4 0 1 1 8-bit uart variable 1 0 2 9-bit uart 3/32 bpclk 1 1 3 9-bit uart variable fig.32 uart control register (scon). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sm0 sm1 sm2 ren tb8 rb8 ti ri
august 1993 50 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 9.3.3 uart i nterrupt registers the uart interface contains four registers for the control of the transmitter and receiver interrupts. one pair of registers (utir and utiv) provide independent control of transmitter interrupts; the other pair of registers (urir and uriv) provide independent control of receiver interrupts. in the following register descriptions x can be replaced by t for transmitter, or r for receiver. 9.3.4 uart t ransmitter /r eceiver i nterrupt r egister (u x ir) these registers have a default value of xx0x0000 b . table 44 description of uxir bits. symbol bit function - uxir.7 reserved - uxir.6 reserved avn uxir.5 autovector. when avn = 0; the transmitter/receiver interrupt is an autovectored interrupt and the processor calculates the appropriate vector from a ?xed vector table. avn = 0 is also the default value. when avn = 1; the transmitter/receiver interrupt is a vectored interrupt and the peripheral must provide an 8-bit vector number. - uxir.4 reserved pir uxir.3 pending interrupt request. this bit is set to a logic 1 when a valid interrupt request has been detected. it is automatically reset by the interrupt acknowledge cycle from the cpu. if pir = 0; there is no pending interrupt request; this is also the default value. pir can be reset by software by writing a logic 0 to this location. ipl2 ipl1 ipl0 uxir.2 uxir.1 uxir.0 interrupt priority level. these three bits determine the interrupt priority level of the interrupt requested by the transmitter/receiver. see table 45. fig.33 uart transmitter/receiver interrupt register (uxir). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -- avn - pir ipl2 ipl1 ipl0
august 1993 51 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 45 selection of transmitter/receiver interrupt priority level. 9.3.5 uart t ransmitter /r eceiver i nterrupt v ector (u x iv) these registers have a default value of 0fh. table 46 description of uxiv bits. ipl2 ipl1 ipl0 priority level 0 0 0 interrupt inhibited; this is also the default value. 0 0 1 level 1 0 1 0 level 2 0 1 1 level 3 1 0 0 level 4 1 0 1 level 5 1 1 0 level 6 1 1 1 level 7 symbol bit function iv.7 to iv.0 utiv.7 to utiv.0 8-bit interrupt vector number. the default value of this register is 0fh. fig.34 uart transmitter/receiver interrupt vector (uxiv). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iv.7 iv.6 iv.5 iv.4 iv.3 iv.2 iv.1 iv.0
august 1993 52 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 10 8-bit general port the port is configured as a quasi-bidirectional port. a port pin is set to input mode by writing a logic 1 to the corresponding general port register (gp) bit. this drives a hard logic 1 to the corresponding output pin for a short period. after this period the logic 1 level is maintained by a weak pull-up transistor, which can be overwritten by an external signal. a read from gp reads the value from the corresponding general port register bit. a read from the general port pad/register (gpp) reads the value from the corresponding port input pin. a write to either gp or gpp writes the value to the port register (gp) from where it is driven to the corresponding port pins. after reset the port is set to input mode. bits 0 to 3 can be used as high current drive outputs at a logic 0. bits 6 and 7 may also be used for i 2 c1 and therefore no internal pull-ups are implemented. 10.1 8-bit general port registers 10.1.1 g eneral p ort r egister (gp) this register is located at address 8000 2073h. 10.1.2 g eneral p ort p ad /r egister (gpp) this register is located at address 8000 2071h. fig.35 general port register (gp). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 fig.36 general port pad/register (gpp). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpp7 gpp6 gpp5 gpp4 gpp3 gpp2 gpp1 gpp0
august 1993 53 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 11 8-bit auxiliary port unused address pins can be used as auxiliary ports. the selection of unused address pins (a23 to a16) for use as auxiliary ports is controlled by the auxiliary port control register (apcon). each bit in apcon controls one address pin. a logic 1 written to apcon.n enables the auxiliary port function of the address pin a(n + 16). the apcon bits and their associated address pins are shown in fig.37. a logic 0 written to apcon.n disables the auxiliary port function and drives the internal address bus to a(n + 16). if bit apcon.n is set, a read from the corresponding bit app.n in the auxiliary port pad/register (app), reads the value from the address pin a(n + 16). a write to app.n when apcon.n is set, drives the value of app.n to the address pin a(n + 16). after reset the auxiliary port function is disabled (apcon = 00h). the auxiliary port is configured as a quasi-bidirectional port in the same way as described for the 8-bit general port. a port pin is set to input mode by writing a logic 1 to the corresponding port register bit. this drives a hard logic 1 to the corresponding output pin for a short period. after this period the logic 1 level is maintained by a weak pull-up transistor, which can be overwritten by an external signal. 11.1 8-bit auxiliary port registers 11.1.1 a uxiliary p ort c ontrol r egister (apcon) this register is located at address 8000 2083h. 11.1.2 a uxiliary p ort p ad /r egister (app) this register is located at address 8000 2081h. fig.37 auxiliary port control register (apcon). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 apcon.7 (a23) apcon.6 (a22) apcon.5 (a21) apcon.4 (a20) apcon.3 (a19) apcon.2 (a18) apcon.1 (a17) apcon.0 (a16) fig.38 auxiliary port/pad register (app). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 app7 app6 app5 app4 app3 app2 app1 app0
august 1993 54 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 12 watchdog timer the p90ce201 contains a watchdog timer. its purpose is to reset the microcontroller, after a programmable time interval, in the event of the microcontroller entering an erroneous processor state. erroneous processor states can be caused by noise or rfi. the watchdog timer consists of a 14-bit prescaler and an 8-bit timer (wdtim). the prescaler is incremented by the basic peripheral clock. wdtim is incremented every 16384 cycles of the basic peripheral clock. it is the value written to wdtim that determines the watchdog timer interval. if the timer interval is exceeded, the watchdog timer overflows and the microcontroller is reset. in order to prevent a timer overflow, the user program must reload the watchdog timer within a time period shorter than the programmed watchdog timer interval. the watchdog timer is controlled by the watchdog control register (wdcon). wdcon can be read and written to by software. after reset, the watchdog timer is disabled and wdcon contains a5h which clears both the prescaler and wdtim. the watchdog timer is enabled by the first write operation to wdcon after reset. a running watchdog timer can only be disabled by resetting the device. wdtim can be read on the fly but can only be written to if wdcon has been loaded with 5ah. a successful write operation to wdtim also clears the prescaler and sets wdcon to 00h in order to prevent further, unintentional, write operations to wdtim. the watchdog timer interval (t) may be calculated as follows: for example, if the basic peripheral clock frequency is 4 mhz, the watchdog timer interval will be within the range 4.1 ms to 1 second. t 256 wdtim value C () 16384 basic peripheral clock frequency --------------------------------------------------------------------------------------- = fig.39 watchdog timer. handbook, full pagewidth mlb253 internal bus write wdtim prescaler (14-bit) wdtim (8-bit) load clearen loaden clear wdcon internal bus clear bpclk to reset circuitry from reset circuitry
august 1993 55 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 13 timers 13.1 general the p90ce201 contains three almost identical, fully independent 16-bit timers (t0, t1 and t2). in the following general description of the timer block, n represents the number of the timer (0, 1 or 2). timer n is a 16-bit timer/counter which is formed by the two 8-bit registers tln and thn. another pair of registers, rcapln and rcaphn, form a 16-bit capture register or a 16-bit reload register. the timers can operate either as a timer or as an event counter. the selection of the clock source for each timer is done in register syscon2 (see table 12). the timers have three operation modes. the differences between the three timers are listed below: table 47 selection of the trigger pulse. mode 1: timer/counter in capture mode mode 2: timer/counter in auto-reload mode mode 3: timer/counter in baud rate generator mode for uart timer 0: operates in all modes with the internal frequency of f xtal /2 or f xtal /32. timer 0 contains a transition detection circuit for the external input. the detection circuitry is controlled by two bits in syscon2; all possible transitions can be monitored. table 47 shows the selection of the trigger pulse. syscon2.3 syscon2.2 transition 0 0 no edge detection 0 1 rising edge detection 1 0 falling edge detection (default value) 1 1 falling and rising edge detection timer 1: operates in all modes with the internal frequency of f xtal /2 or f xtal /32. transition detection for the external input is ?xed to falling edge detection. timer 2: operates in all modes with the internal frequency of f xtal /2 or bpclk/4. transition detection for the external input is ?xed to falling edge detection. 13.2 timer operating modes the timer control register (tncon) controls the selection of the timer operating modes; this is described in section 13.3.1 timer control register (tncon). 13.2.1 c apture mode in the capture mode there are two options which are selected by the exenn bit in tncon. if exenn = 0, then timer n is a 16-bit timer/counter which on overflow sets the overflow bit tfn. the overflow can be used to generate an interrupt. if exenn = 1, then timer n operates in the same way as exenn = 0 but with the additional feature that a valid transition at the external input tn causes the current value in timer n registers (tln and thn) to be captured into registers rcapln and rcaphn, respectively. the transition at input tn also causes the exfn bit in tncon to be set; this can also be used to generate an interrupt. 13.2.2 a uto - reload mode in the auto-reload mode there are two options which are selected by the exenn bit in tncon. if exenn = 0, then a timer n overflow sets the tfn bit and causes the timer n registers to be reloaded with the 16-bit value held in registers rcapln and rcaphn. this 16-bit value is preset by software. the overflow can be used to generate an interrupt. if exenn = 1, then timer n operates as above but with the additional feature that a valid transition at the external input tn triggers the 16-bit reload and sets the exfn bit. the transition can also be used to generate an interrupt. 13.2.3 b aud r ate g enerator mode the baud rate generator mode for the uart is selected by rclkn and/or tclkn in tncon. overflows of timer n can be used or generating baud rates for transmit and receive of the uart in its modes 1 and 3. see table 50. the baud rate generation mode is similar to the auto-reload mode, in that a rollover in thn causes the timer n registers to be reloaded with the 16-bit value held in registers rcapln and rcaphn, which are preset by software. the baud rate for the uart is determined by timer ns overflow rate as specified below. baud rate timer n overflow rate 16 ---------------------------------------------------------- =
august 1993 56 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 timer n can be configured for either timer or counter operation. in timer operation the internal timer frequency (f int ) is given by f xtal /2, f xtal /32 or bpclk/4. the baud rate may be calculated as follows: in this mode an overflow of timer n does not set tfn and does not generate an interrupt. if exenn = 1, a valid transition at input pin tn sets exfn and can be used to generate an interrupt. baud rate f int 16 65536 rcapnh, rcapnl () C () ------------------------------------------------------------------------------------------------------ - = fig.40 timer/counter in capture mode - mode 1. handbook, full pagewidth mlb008 tln (8 bits) trn control thn (8 bits) rcapnl rcapnh exfn tfn timer n interrupt exenn control c/tn = 0 c/tn = 1 prescaler osc transition detector external pin tn capture
august 1993 57 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 fig.41 timer/counter in auto-reload mode - mode 2. handbook, full pagewidth mlb009 tln (8 bits) trn control thn (8 bits) rcapnl rcapnh exfn tfn timer n interrupt exenn control c/tn = 0 c/tn = 1 prescaler osc transition detector external pin tn reload fig.42 timer/counter in baud rate generator mode - mode 3. handbook, full pagewidth mlb010 tln (8 bits) trn control thn (8 bits) rcapnl rcapnh exfn timer n interrupt exenn control c/tn = 0 c/tn = 1 prescaler osc transition detector external pin tn reload uart clock
august 1993 58 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 13.3 timer registers 13.3.1 t imer c ontrol r egister (tncon) the timer control register (tncon) controls the selection of the timer operating modes and the uart clock source. table 48 description of tncon bits. symbol bit function tfn tncon.7 timer n over?ow ?ag. set by a timer n over?ow and must be cleared by software. tfn will not be set when either rclkn = 1 or tclkn = 1. exfn tncon.6 timer n external ?ag. set when either a capture or reload is caused by a negative transition on external input tn and when exenn = 1. exfn must be cleared by software. rclkn tncon.5 receive clock ?ag. when set, causes the uart to use timer n over?ow pulses for its receive clock in modes 1 and 3. see table 50. tclkn tncon.4 transmit clock ?ag. when set, causes the uart to use timer n over?ow pulses for its transmit clock in modes 1 and 3. see table 50. exenn tncon.3 timer n external enable ?ag. when set, allows a capture or reload to occur as a result of a negative transition on external input tn, if timer n is not being used to clock the uart. exenn = 0 causes timer 2 to ignore events at external input tn. trn tncon.2 start/stop control. trn = 1 starts timer n; trn = 0 stops the timer. c/ tn tncon.1 timer or counter select. c/ tn = 0 selects the internal timer. c/ tn = 1 selects the external event counter (edge triggered). cp/ rln tncon.0 capture/reload ?ag. when set, captures will occur on valid transitions at external input tn, if exen2 = 1. when cleared, auto-reloads will occur upon either timer n over?ows or valid transitions at tn, if exenn = 1. when either rclkn = 1 or tclkn = 1, this bit is ignored and the timer is forced to auto-reload on a timer n over?ow. fig.43 timer control registers (tncon). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tfn exfn rclkn tclkn exenn trn c/ tn cp/ rln
august 1993 59 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 49 selection of timer n operating modes. table 50 uart clock source for receive and transmit - modes 1 and 3. note 1. these combinations lead to the addition of clock pulses from different timers giving an irregular baud rate clock and therefore should not be used. rclkn + tclkn cp/ rl n trn mode 0 0 1 16-bit automatic reload 0 1 1 16-bit capture 1 x 1 baud rate generator xx0off rclk2 rclk1 rclk0 uart clock source tclk2 tclk1 tclk0 0 0 0 none 0 0 1 timer 0 0 1 0 timer 1 1 0 0 timer 2 x 1 1 not usable, see note 1 1 x 1 not usable, see note 1 1 1 x not usable, see note 1
august 1993 60 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 13.3.2 t imer i nterrupt r egister (tnir) each timer contains a register for the control of interrupts. table 51 description of tnir bits. table 52 selection of interrupt priority level. symbol bit function - tnir.7 reserved - tnir.6 reserved avn tnir.5 autovector. when avn = 0; the timer interrupt is an autovectored interrupt and the processor calculates the appropriate vector from a ?xed vector table. avn = 0 is also the default value. when avn = 1; the timer interrupt is a vectored interrupt and the peripheral must provide an 8-bit vectored interrupt. - tnir.4 reserved pir tnir.3 pending interrupt request. this bit is set to a logic 1 when a valid interrupt request has been detected. it is automatically reset by the interrupt acknowledge cycle from the cpu. if pir = 0, there is no pending interrupt request; this is also the default value. the pir bit can be reset by software by writing a logic 0 to this location. ipl2 ipl1 ipl0 tnir.2 tnir.1 tnir.0 interrupt priority level. these three bits determine the interrupt priority level of the interrupt requested by the timer. see table 52. ipl2 ipl1 ipl0 priority level 0 0 0 interrupt inhibited; this is also the default value. 0 0 1 level 1 0 1 0 level 2 0 1 1 level 3 1 0 0 level 4 1 0 1 level 5 1 1 0 level 6 1 1 1 level 7 fig.44 timer interrupt register (tnir). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -- avn - pir ipl2 ipl1 ipl0
august 1993 61 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 13.3.3 t imer i nterrupt v ector (tniv) table 53 description of tniv bits. symbol bit function iv.7 to iv.0 tniv.7 to tniv.0 8-bit interrupt vector number. the default value of this register is 0fh. fig.45 interrupt vector register (tniv). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iv.7 iv.6 iv.5 iv.4 iv.3 iv.2 iv.1 iv.0
august 1993 62 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 14 electromagnetic compatibility (emc) improvements primary attention has been paid to the reduction of electromagnetic emission of the microcontroller. the following features result in a reduction of the electromagnetic emission and additionally improve the electromagnetic susceptibility: two supply voltage pins (v dd1 and v dd2 ) and two ground pins (v ss1 and v ss2 ) are provided. v dd1 and v ss1 are adjacent pins located on one side of the package; v dd2 and v ss2 are also adjacent pins located diagonally opposite the v dd1 and v ss1 pins. separate power supply pins for internal logic/memory interface and peripheral pins (quiet port) internal decoupling capacitance improves the emc radiation behaviour and the emc immunity external capacitors are to be connected as close as possible between pins v dd1 and v ss1 and also v dd2 and v ss2 . ceramic chip capacitors are recommended (100 nf). 15 electrical specifications 15.1 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. this value is based on the maximum allowable die temperature and the thermal resistance of the package; not on device power consumption. symbol parameter min. max. unit v dd supply voltage - 0.5 + 6.5 v v i input voltage on any pin with respect to ground (v ss ) - 0.5 v dd + 0.5 v p tot total power dissipation; see note 1 - 0.75 w t stg storage temperature - 65 + 150 c t amb operating ambient temperature - 25 + 85 c
august 1993 63 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 15.2 dc characteristics v dd =5v 10%; v ss =0v; t amb = - 25 to + 85 c; all voltages with respect to v ss unless otherwise speci?ed. symbol parameter conditions min. max. unit supply v dd supply voltage 4.5 5.5 v i dd supply current operating v dd = 5.5 v; f clk = 24 mhz note 1 - 70 ma r rst reset pull-down resistor 50 150 k w inputs v il low level input voltage (except scln and sdan) - 0.5 0.8 v v il1 low level input voltage scln and sdan note 2 - 0.5 1.5 v v ih high level input voltage (except reset, xtal1, scln, sdan) 2.0 v dd + 0.5 v v ih1 high level input voltage reset, xtal1 0.7v dd + 0.1 v dd + 0.5 v v ih2 high level input voltage scln, sdan note 2 3.0 6.0 v i il low level input current gp0-5, a16-23 in port mode, intn0 - 7 v in = 0.45 v -- 50 m a i tl input current high-to-low transition for externally driven port pins (except gp6 and gp7) v in = 2.0 v -- 650 m a i li input leakage current d0 to d7 0.45 v v in v dd - 10 m a i li1 input leakage current scln, sdan 0.4 v v in 4.95 v note 2 - 10 m a outputs v ol low level output voltage (except gp0-3, scln,sdan) i ol = 1.6 ma; note 3 - 0.45 v v ol1 low level output voltage gp0-3 i ol = 6.4 ma; note 3 ii ol = 20 ma; note 3 - 0.45 1.2 v v v ol2 low level output voltage scln, sdan i ol = 3.0 ma; notes 2 and 3 i ol = 60 ma; notes 2 and 3 - - 0.4 0.6 v v v oh high level output voltage (except scln,sdan) i oh = - 60 m a 2.4 - v
august 1993 64 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 notes 1. the operating supply current is measured during the stop instruction executed immediately after reset. all inputs are driven high and outputs are loaded with c l = 50 pf, r = 1 m w ; xtal1 is driven with t r =t f = 5 ns; v il =v ss + 0.5 v; v ih1 =v dd - 0.5 v; xtal2 not connected. 2. the parameter meets the i 2 c-bus specification for standard mode and fast mode devices. 3. under steady state (non-transient) conditions, i ol must be externally limited as shown in table 54. if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. table 54 maximum i ol values. 15.3 ac characteristics v dd =5v 10%; v ss = 0 v; t clclmin = 1/f clkmax = 42 ns; t amb = - 25 to + 85 c. 15.3.1 ac testing input and output waveforms . ac test inputs are driven at 2.4 v for a logic 1 and 0.45 v for a logic 0. timing measurements are taken at 2.0 v for a logic 1 and 0.8 v for a logic 0. see fig.46(a). the float state is defined as the point at which the pin sinks 3.2 ma or sources 400 m a at the voltage test levels. see fig.46(b). parameter max unit maximum i ol per port pin 10 ma maximum i ol per high drive port pin (gp0 - gp3) 20 ma maximum total i ol for all output pins 100 ma fig.46 ac testing input, output waveform (a) and float waveform (b). handbook, full pagewidth mla769 2.0 v 0.8 v 2.4 v 0.45 v 2.0 v 0.8 v float (b) (a) 2.4 v 0.45 v 2.0 v 0.8 v 2.0 v 0.8 v test points
august 1993 65 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 15.3.2 e xternal clock drive xtal1 table 55 external clock drive xtal1. symbol parameter min. max. unit t clcl clock period 42 250 ns t chcx high time 15 t clcl - t clcx ns t clcx low time 15 t clcl - t chcx ns t clch rise time - 20 ns t chcl fall time - 20 ns fig.47 external clock drive xtal1. handbook, full pagewidth mla856 t chcx t clcx t clcl t clch t chcl v ih1 v ih1 0.8 v 0.8 v v ih1 v ih1 0.8 v 0.8 v
august 1993 66 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 15.3.3 e xternal memory interface table 56 external memory read cycle timing. note 1. ws is the number of additional wait states access time values. see table 11 in section 6. symbol parameter min. max. unit t avsl address valid to csromn/csramn low t clcl - 25 - ns t sldv csromn/csramn low to data valid; note 1 - (2 + ws/2)t clcl - 65 ns t axdx address invalid to data invalid 0 - ns t avdv address valid to data valid; note 1 - (2 + ws/2)t clcl - 65 ns t shax csromn/csramn high to address invalid t clcl - 15 - ns t shdx csromn/csramn high to data invalid 0 - ns fig.48 external memory read cycle. handbook, full pagewidth mlb013 address csramn csromn d0 d7 t sldv lsb data r/wn t shax axdx t t avsl t avdv t shdx msb data address 1 even address
august 1993 67 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 table 57 external memory write cycle timing. note 1. ws is the number of additional wait states access time values. see table 11 in section 6. symbol parameter min. unit t avsl address valid to csromn/csramn low t clcl - 25 ns t wlsl rwn low to csromn/csramn low t clcl - 25 ns t shwh csromn/csramn high to rwn high t clcl - 15 ns t slsh csromn/csramn low; note 1 (2 + ws/2)t clcl - 15 ns t shax csromn/csramn high to address invalid t clcl - 15 ns t qvsh data set-up to csromn/csramn high; note 1 (2 + ws/2)t clcl - 20 ns t shqx csromn/csramn high to data invalid t clcl - 15 ns fig.49 external memory write cycle. handbook, full pagewidth mlb123 address csramn csromn d0 d7 t slsh r/wn t shwh qvsh t t avsl t shax t shqx lsb address msb address t wlsl
august 1993 68 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 15.3.4 f ast i 2 c- bus timing . table 58 fast i 2 c-bus timing. notes 1. a device must internally provide a hold time of at least 300 ns for the sda signal, referenced to v ihmin of the scl signal, in order to bridge the undefined region of the falling edge of scl. the maximum t hd;dat has to be met only if the device does not stretch the scl low period (t low ). 2. a fast-mode i 2 c-bus device can be used in a 0-to-100 kbit/s i 2 c-bus system and then the requirement t su;dat > 250 ns must be fulfilled. this will automatically be the case if the device does not stretch the low period of the scl signal. but if such a device stretches the low period of the scl signal, it must output the next data bit to the sda line (t rdmax + t su;dat ) = 1000 + 250 = 1250 ns before the scl line is released according to the existing 0-to-100 kbit/s i 2 c-bus specification. 3. c b = total capacitance value of one bus line in pf. symbol parameter min. max. unit f scl scl clock frequency 0 400 khz t buf bus free time between a stop and start condition 1300 - ns t hd; sta hold time (repeated) start condition 600 - ns t low low period of the scl clock 1300 - ns t high high period of the scl clock 600 - ns t su; sta set-up time (repeated) start 600 - ns t hd; dat data hold time (note 1) 0 900 ns t su; dat data set-up time (note 2) 100 - ns t rc ;t rd rise time of both sda and scl lines (note 3) (20 + 0.1cb) 300 ns t fc; t fd fall time of both sda and scl lines (note 3) (20 + 0.1cb) 300 ns t su; sto set-up time for stop condition 600 - ns c b capacitive load of each bus line - 400 pf
august 1993 69 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 handbook, full pagewidth t rd t fd t rc t fc t hd;sta t low t high t su;dat1 t hd;dat t su;dat2 t su;dat3 0.7 v dd 0.3 v dd t su;sto t buf t su;sta sda (input / output) scl (input / output) start condition repeated start condition stop condition start or repeated start condition 0.7 v dd 0.3 v dd mbc482 fig.50 fast i 2 c-bus interface timing.
august 1993 70 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 15.3.5 uart s hift r egister mode timing table 59 basic peripheral clock set to 4 mhz; c l =80pf. symbol parameter min. max. unit t xlxl serial port clock cycle time 1000 - ns t qvxh output data set-up to clock rising edge 700 - ns t xhqx output data hold after clock rising edge 50 - ns t xhdx input data hold after clock rising edge 0 - ns t xhdv clock rising edge to input data valid - 700 ns fig.51 uart shift register mode timing. handbook, full pagewidth mlb124 clock 7 6 5 4 3 2 1 0 valid write to sbuf output data clear ri input data t xlxl t xhqx t qvxh t xhdv t xhdx set ri set ti valid valid valid valid valid valid valid
august 1993 71 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 16 register map the internal register map of the p90ce201 is summarized in the following tables. address (hex) symbol register system registers 8000 1000 syscon1h syscon1 system control register 1 high r/w 8000 1001 syscon1l system control register 1 low r/w 8000 1002 syscon2h syscon2 system control register 2 high r/w 8000 1003 syscon1l system control register 2 low r/w 8000 1004 to 800 101f reserved interrupt registers 8000 1020 reserved 8000 1021 lir7 latched interrupt 7 register r/w 8000 1022 reserved 8000 1023 liv7 latched interrupt 7 vector r/w 8000 1024 reserved 8000 1025 lir6 latched interrupt 6 register r/w 8000 1026 reserved 8000 1027 liv6 latched interrupt 6 vector r/w 8000 1028 reserved 8000 1029 lir5 latched interrupt 5 register r/w 8000 102a reserved 8000 102b liv5 latched interrupt 5 vector r/w 8000 102c reserved 8000 102d lir4 latched interrupt 4 register r/w 8000 102e reserved 8000 102f liv4 latched interrupt 4 vector r/w 8000 1030 reserved 8000 1031 lpcrh port control register bit 7 to 4 r/w 8000 1032 reserved 8000 1033 lpph port pad/control register bit 7 to 4 r/w 8000 1034 to 8000 1040 reserved 8000 1041 lir3 latched interrupt 3 register r/w 8000 1042 reserved 8000 1043 liv3 latched interrupt 3 vector r/w 8000 1044 reserved 8000 1045 lir2 latched interrupt 2 register r/w 8000 1046 reserved 8000 1047 liv2 latched interrupt 2 vector r/w
august 1993 72 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 8000 1048 reserved 8000 1049 lir1 latched interrupt 1 register r/w 8000 104a reserved 8000 104b liv1 latched interrupt 1 vector r/w 8000 104c reserved 8000 104d lir0 latched interrupt 0 register r/w 8000 104e reserved 8000 104f liv0 latched interrupt 0 vector r/w 8000 1050 reserved 8000 1051 lpcrl port control register bit 3 to 0 r/w 8000 1052 reserved 8000 1053 lppl port pad/control register bit 3 to 0 r/w 8000 1054 to 8000 105f reserved i 2 c registers 8000 2000 reserved 8000 2001 s1dat i 2 c1 data register r/w 8000 2002 reserved 8000 2003 s1adr i 2 c1 address register r/w 8000 2004 reserved 8000 2005 s1sta i 2 c1 status register r 8000 2006 reserved 8000 2007 s1con i 2 c1 control register r/w 8000 2008 reserved 8000 2009 s1ir i 2 c1 interrupt register r/w 8000 200a reserved 8000 200b s1iv i 2 c1 interrupt vector r/w 8000 200c to 8000 2010 reserved 8000 2011 s2dat i 2 c2 data register r/w 8000 2012 reserved 8000 2013 s2adr i 2 c2 address register r/w 8000 2014 reserved 8000 2015 s2sta i 2 c2 status register r 8000 2016 reserved 8000 2017 s2con i 2 c2 control register r/w 8000 2018 reserved 8000 2019 s2ir i 2 c2 interrupt register r/w 8000 201a reserved 8000 201b s2iv i 2 c2 interrupt vector r/w 8000 201c to 8000 201f reserved address (hex) symbol register
august 1993 73 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 uart registers 8000 2020 reserved 8000 2021 sbuf uart transmit/receive register r/w 8000 2022 reserved 8000 2023 scon uart control register r/w 8000 2024 reserved 8000 2025 urir uart receiver interrupt register r/w 8000 2026 reserved 8000 2027 uriv uart receiver interrupt vector r/w 8000 2028 reserved 8000 2029 utir uart transmitter interrupt register r/w 8000 202a reserved 8000 202b utiv uart transmitter interrupt vector r/w 8000 202c to 8000 202f reserved timers registers 8000 2030 th0 t0 timer 0 high order register r/w 8000 2031 tl0 timer 0 low order register r/w 8000 2032 rcaph0 rcap0 timer 0 reload/capture high order register r/w 8000 2033 rcapl0 timer 0 reload/capture low order register r/w 8000 2034 reserved 8000 2035 t0con timer 0 control register r/w 8000 2036 reserved 8000 2037 t0ir timer 0 interrupt register r/w 8000 2038 reserved 8000 2039 t0iv timer 0 interrupt vector r/w 8000 203a to 800 203f reserved 8000 2040 th1 t1 timer 1 high order register r/w 8000 2041 tl0 timer 1 low order register r/w 8000 2042 rcaph1 rcap1 timer 1 reload/capture high order register r/w 8000 2043 rcapl1 timer 1 reload/capture low order register r/w 8000 2044 reserved 8000 2045 t1con timer 1 control register r/w 8000 2046 reserved 8000 2047 t1ir timer 1 interrupt register r/w 8000 2048 reserved 8000 2049 t1iv timer 1 interrupt vector r/w 8000 204a to 8000 204f reserved 8000 2050 th2 t2 timer 2 high order register r/w 8000 2051 tl2 timer 2 low order register r/w address (hex) symbol register
august 1993 74 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 8000 2052 rcaph2 rcap2 timer 2 reload/capture low order register r/w 8000 2053 rcapl2 timer 2 reload/capture low order register r/w 8000 2054 reserved 8000 2055 t2con timer 2 control register r/w 8000 2056 reserved 8000 2057 t2ir timer 2 interrupt register r/w 8000 2058 reserved 8000 2059 t2iv timer 2 interrupt vector r/w 8000 205a to 8000 205f reserved watchdog registers 8000 2060 reserved 8000 2061 wdtim watchdog timer register r/w 8000 2062 reserved 8000 2063 wdcon watchdog control register r/w 8000 2064 to 8000 206f reserved general port registers 8000 2070 reserved 8000 2071 gpp port pad/register r/w 8000 2072 reserved 8000 2073 gp port register r/w 8000 2074 to 8000 207f reserved auxiliary port registers 8000 2080 reserved 8000 2081 app auxiliary port pad/register r/w 8000 2082 reserved 8000 2083 apcon auxiliary port control register r/w 8000 2084 to 8000 208f reserved address (hex) symbol register
august 1993 75 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 17 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-2 95-02-04 97-08-01 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d e q e a 1 a l p detail x l (a ) 3 b 19 y c e h a 2 d z d a z e e v m a 1 64 52 51 33 32 20 x pin 1 index b p d h b p v m b w m w m 0 5 10 mm scale qfp64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot319-2 a max. 3.20
august 1993 76 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 18 soldering 18.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 18.2 re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 18.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
august 1993 77 philips semiconductors product speci?cation 16-bit microcontroller p90ce201 19 definitions 20 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 21 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.

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